同學的加分題

以下為1個2位元之比較器



把卡諾圖化簡以後會得到:f = a'b'cd' + bc'd + abd + ac'








(上圖程式碼)用產生之訊號輸出如圖
輸入訊號與a、b、c、d相關，d的訊號是10101010...，c的訊號是0011001100...，c = 2d，同理，a = 2b = 4c = 8d。所以f = 1即訊號的up。

12/8 Behaviornl Model

module D_filp_flop ( q , data_in , dk )
input data_in , clk;
output q;
reg q;

always@( clk )
begin
if ( clk == 0 )
q = q;
else
q = data_in;
end
endmodule

延遲

2位元比較器

module conmpare_2_str(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
wire w1,w2,w3,w4,w5,w6,w7;
or(A_lt_B,w1,w2,w3);
nor(A_gt_B,A_lt_B,A_eq_B);
and(A_eq_B,w4,w5);
and(w1,w6,B1);
and(w2,w6,w7,B0);
and(w3,w7,B0,B1);
not(w6,A1);
not(w7,A0);
xnor(w4,A1,B1);
xnor(w5,A0,B0);
endmodule

AOI_4_unit

module AOI_4_unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);

4位元全加法器

module top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;

system_clock #200 clock1(x_in1);
system_clock #100 clock2(x_in2);
system_clock #50 clock3(x_in3);
system_clock #25 clock4(x_in4);

AOI_Unit m1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module AOI_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule




module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10/13 Verilog structural......

module Add_half (sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor (sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule