AOI_4_unit

module AOI_4_unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);

4位元全加法器

module top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;

system_clock #200 clock1(x_in1);
system_clock #100 clock2(x_in2);
system_clock #50 clock3(x_in3);
system_clock #25 clock4(x_in4);

AOI_Unit m1(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module AOI_Unit(y_out,x_in1,x_in2,x_in3,x_in4);
input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;
and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule




module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

10/13 Verilog structural......

module Add_half (sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor (sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

SynaptiCAD 使用簡介

http://www.dyu.edu.tw/~cschen/CODA/doc/syncad.doc

課程中會用到的工具軟體下載.....SynaptiCAD 試用版 下載

1. 按滑鼠右鍵, 選 [另存目標] 到硬碟目錄, 再點選執行 解壓縮 到您要的目錄......http://www.dyu.edu.tw/~cschen/Verilog%20Computer%20Design/SynaptiCAD.exe

2. 點選執行 SYNCAD.EXE

//code

module top;
wire a,b;
reg c;
system_clock #100 clock1(a);
system_clock#50 clock2(b);
always
#1 c=a&b;
endmodule

//text_bench
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial

clk=0;
always
begin

#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end

always @ (posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

波形圖